Archives
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| 2020.08.06 |
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Proper Layout Solves Most Power MOSFET Design Problems |
| 2015.03.25 |
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Forza Silicon selects Silicon Frontline’s P2P for Fast, Easy IR Drop and Resistance Mapping |
| 2013.09.05 |
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Lattice Semiconductor Selects Silicon Frontline for Electrostatic Discharge (ESD) Analysis |
| 2012.03.06 |
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Integrated Device Technology (IDT) Picks Silicon Frontline to Improve Power Device Reliability and Efficiency |
| 2012.02.02 |
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X-FAB Uses Silicon Frontline’s Post-Layout Extraction Software to Enhance its Advanced Mixed-Signal Process Design Kit (PDK) |
| 2011.05.26 |
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Silicon Frontline Addresses EDA Industry Bottleneck, Promotes Guaranteed Accurate 3D Post-Layout Extraction at Design Automation Conference |
| 2011.05.18 |
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Silicon Frontline Announces First Commercial 3D Hierarchical Extractor |
| 2011.05.05 |
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Silicon Frontline Promotes Guaranteed Accurate 3D Post-Layout Extraction for Power Devices and Image Sensors at Upcoming Events |
| 2011.02.28 |
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Faraday Picks Silicon Frontline’s F3D for Accurate Post-Layout 3D Extraction of Analog and Digital Converters |
| 2011.01.25 |
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Silicon Frontline Ends 2010 with New Customers and Most Successful Quarter to Date |
| 2010.10.25 |
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CHiL Semiconductor Picks Silicon Frontline for Power Device Design and Efficiency (http://www.marketwire.com) |
| 2010.10.18 |
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Silicon Frontline Continues on Path to Success, Verifies Hundreds of Designs with Its Post-Layout EDA Software. (electronicspecifier.com) |
| 2010.06.10 |
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TSMC 28nm analog and mixed-signal referenced flow includes Silicon Frontline’s F3D parasitic extraction software. |
| 2010.05.25 |
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UMC uses Silicon Frontline’s field solver to generate reference extraction data. |
| 2010.03.01 |
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Triune Systems picks Silicon Frontline Technology to optimize power device design, reduce carbon footprint. |
| 2009.11.19 |
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Aptina picks Silicon Frontline’s post-layout verification EDA software. |
| 2009.11.05 |
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Startup launches post-layout verification tools (EETimes.com) |
| 2009.07.09 |
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Silicon Frontline Technology’s software qualifies for TSMC’s Unified Interconnect Modeling Format iRCX for 40 and 65nm processes. |
| 2009.06.24 |
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UMC qualifies Silicon Frontline’s parasitic extraction software for 40 and 65nm processes. |
| 2009.06.23 |
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Silicon Frontline Aims at Post-Layout Verification (SCDsource) |
| 2009.05.12 |
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Silicon Frontline F3D and R3D product announcement. |
