2021.04.09 HDL Design House selects Silicon Frontline’s P2P Software for Fast, Easy IR Drop and Resistance Mapping


2020.08.06 Proper Layout Solves Most Power MOSFET Design Problems
2015.03.25 Forza Silicon selects Silicon Frontline’s P2P for Fast, Easy IR Drop and Resistance Mapping
2013.09.05 Lattice Semiconductor Selects Silicon Frontline for Electrostatic Discharge (ESD) Analysis
2012.03.06 Integrated Device Technology (IDT) Picks Silicon Frontline to Improve Power Device Reliability and Efficiency
2012.02.02 X-FAB Uses Silicon Frontline’s Post-Layout Extraction Software to Enhance its Advanced Mixed-Signal Process Design Kit (PDK)
2011.05.26 Silicon Frontline Addresses EDA Industry Bottleneck, Promotes Guaranteed Accurate 3D Post-Layout Extraction at Design Automation Conference
2011.05.18 Silicon Frontline Announces First Commercial 3D Hierarchical Extractor
2011.05.05 Silicon Frontline Promotes Guaranteed Accurate 3D Post-Layout Extraction for Power Devices and Image Sensors at Upcoming Events
2011.02.28 Faraday Picks Silicon Frontline’s F3D for Accurate Post-Layout 3D Extraction of Analog and Digital Converters
2011.01.25 Silicon Frontline Ends 2010 with New Customers and Most Successful Quarter to Date
2010.10.25 CHiL Semiconductor Picks Silicon Frontline for Power Device Design and Efficiency (
2010.10.18 Silicon Frontline Continues on Path to Success, Verifies Hundreds of Designs with Its Post-Layout EDA Software. (
2010.06.10 TSMC 28nm analog and mixed-signal referenced flow includes Silicon Frontline’s F3D parasitic extraction software.
2010.05.25 UMC uses Silicon Frontline’s field solver to generate reference extraction data.
2010.03.01 Triune Systems picks Silicon Frontline Technology to optimize power device design, reduce carbon footprint.
2009.11.19 Aptina picks Silicon Frontline’s post-layout verification EDA software.
2009.11.05 Startup launches post-layout verification tools (
2009.07.09 Silicon Frontline Technology’s software qualifies for TSMC’s Unified Interconnect Modeling Format iRCX for 40 and 65nm processes.
2009.06.24 UMC qualifies Silicon Frontline’s parasitic extraction software for 40 and 65nm processes.
2009.06.23 Silicon Frontline Aims at Post-Layout Verification (SCDsource)
2009.05.12 Silicon Frontline F3D and R3D product announcement.