Welcome to Silicon Frontline.
Unparalleled leadership in Power Device Analysis and IR Drop & EM Analysis
- Power Device Analysis: Rdson calculation, Current Density & IR Drop Analysis, EM Verification, Gate delay Analysis, transient operation of power device and full chip, Transient Electro-thermal Analysis
- IR Drop & EM Analysis: Resistance Mapping highlights weak points in networks, point to point resistance, Pre and Post LVS analysis, Static and dynamic analysis capabilities, Extremely simple set-up
Key Performance in ESD Analysis and Parasitic Extraction
- ESD Analysis: Chip level Analysis providing HBM, CDM and MM support, Supports TLP measurements, Highlights non-esd device failures, Reports voltage, current density and resistances for all ESD events
- Parasitic Extraction: Guaranteed Accurate parasitic extraction, user controlled accuracy achievable, Full chip capacity, Supports standard design flows, Supports Manufacturing Effects, Provides distributed Extraction
Upcoming Events
CDNLive Silicon Valley 2019 · Santa Clara, CA
April 2-April 3, 2019
Santa Clara Convention Center
IEW Symposium · Monterey, CA, USA
March 31-April 4, 2019
2019 International ESD Workshop IEW
DAC · Las Vegas, Nevada
June 3-June 5, 2019
Design Automation Conference
ESD Symposium · Riverside, California
September 16-September 18, 2019