Nanometer process technologies permit designers to develop innovative circuits, delivering high-performance functionality and incorporating logic, memory, analog and RF on a single CMOS die. Too often, though, out-of-date layout verification or analysis methodologies prevent designers achieving the full capabilities of the process.

Incomplete verification coverage or inaccurate analysis force designers to add large guardbands, and to sign off with only partial layout verification completed. Performance and yield impact often require expensive silicon debug, redesign and respins to repair.

For designers tired of the constraints forced on them by inefficient and inaccurate layout verification, H3D is a hierarchical extraction tool, delivering superior sub-linear performance, with guaranteed 3D accuracy, for fullchip verification. Compared to traditional tools that require designers to compromise coverage and precision, H3D delivers full-chip guaranteed accuracy, permitting stringent schedules to be met with confidence.

H3D Datasheet

RSS 2.0 feed. Both comments and pings are currently closed.

Comments are closed.