For Release June 30, 2009
UMC Qualifies Silicon Frontline’s Parasitic Extraction Software for 40 and 65nm Processes
F3D post-layout verification software guarantees accuracy and high performance
UMC qualified Silicon Frontline’s F3D for post-layout verification because it guarantees accuracy and high performance by using rigorous 3D technology to extract parasitics. Users can specify the level of accuracy desired, net by net, at the block level or with regular expressions. By guaranteeing accuracy, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.
"Qualifying design tools such as Silicon Frontline’s F3D aids our customers in choosing the software they need to design complex, high performance ICs and to confidently achieve silicon success," said Stephen Fu, IPDS director, at UMC. "The combination of F3D technology with our advanced manufacturing processes, gives customers a more predictable and smoother flow to silicon success.”
“We are pleased to have one of the world’s leading foundries, UMC, support our 3D extraction software for post-layout verification of designs targeting its advanced processes,” said Yuri Feinberg, CEO. “With our software, UMC customers can experience Guaranteed Accuracy with full-chip capacity and performance.”
Silicon Frontline announced the company and its first EDA software products last month.
F3D is ideally suited for sensitive analog and AMS circuits where coupling is a challenge – ADCs, DACs, circuits with differential signals, MIM/MOMCaps and 3D devices, image sensors, RF and high speed designs and for circuits manufactured at advanced technology nodes, such as 65 and 45nm.
UMC (NYSE: UMC, TSE: 2303) is a leading global
semiconductor foundry that provides advanced technology and manufacturing
services for applications spanning every major sector of the IC industry. UMC's
customer-driven foundry solutions allow chip designers to leverage the strength
of the company's leading-edge processes, which include production proven 65nm,
45/40nm, mixed signal/RFCMOS, and a wide range of specialty technologies.
Production is supported through 10 wafer manufacturing facilities that include
two advanced 300mm fabs; Fab 12A in
About Silicon Frontline
Silicon Frontline Technology, Inc. provides post-layout verification software that is Guaranteed Accurate and works with existing design flows from major EDA vendors. Using new 3D technology, the company’s software products improve silicon quality for standard and advanced nanometer processes. For more information please visit www.siliconfrontline.com.
Frontline Technology is headquartered at
Georgia Marszalek, ValleyPR LLC, +1 650 345 7477, Georgia@ValleyPR.com
Notes to editors:
Acronyms and Definitions
CAD: Computer-Aided Design
EDA: Electronic Design Automation
TCAD: Technology Computer-Aided Design
All trademarks and tradenames are the property of their respective holders.