Silicon Frontline - providing electrical and physical verification of IC layouts

Welcome to Silicon Frontline.

Unparalleled leadership in Power Device Analysis and IR Drop & EM Analysis

  • Power Device Analysis: Rdson calculation, Current Density & IR Drop Analysis, EM Verification, Gate delay Analysis, transient operation of power device and full chip, Transient Electro-thermal Analysis
  • IR Drop & EM Analysis: Resistance Mapping highlights weak points in networks, point to point resistance, Pre and Post LVS analysis, Static and dynamic analysis capabilities, Extremely simple set-up

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Key Performance in ESD Analysis and Parasitic Extraction

  • ESD Analysis: Chip level Analysis providing HBM, CDM and MM support,  Supports TLP measurements, Highlights non-esd device failures, Reports voltage, current density and resistances for all ESD events
  • Parasitic Extraction: Guaranteed Accurate parasitic extraction, user controlled accuracy achievable, Full chip capacity, Supports standard design flows, Supports Manufacturing Effects, Provides distributed Extraction

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Upcoming Events

Announcements and Upcoming Events

Silicon Frontline introduces ERCheck

Provides electrical rule checking with built in ESD checks. Learn more »


Silicon Frontline is attending the following conferences:

ISPSD Symposium · Sapporo, Japan
May 29-June 1, 2017

DAC · Austin, TX
June 19-June 21, 2017

ESD Symposium · Tuscon, AZ
September 10-September 15, 2017