Silicon Frontline - providing electrical and physical verification of IC layouts

Welcome to Silicon Frontline.

Unparalleled leadership in Power Device Analysis and IR Drop & EM Analysis

  • Power Device Analysis: Rdson calculation, Current Density & IR Drop Analysis, EM Verification, Gate delay Analysis, transient operation of power device and full chip, Transient Electro-thermal Analysis
  • IR Drop & EM Analysis: Resistance Mapping highlights weak points in networks, point to point resistance, Pre and Post LVS analysis, Static and dynamic analysis capabilities, Extremely simple set-up

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Key Performance in ESD Analysis and Parasitic Extraction

  • ESD Analysis: Chip level Analysis providing HBM, CDM and MM support,  Supports TLP measurements, Highlights non-esd device failures, Reports voltage, current density and resistances for all ESD events
  • Parasitic Extraction: Guaranteed Accurate parasitic extraction, user controlled accuracy achievable, Full chip capacity, Supports standard design flows, Supports Manufacturing Effects, Provides distributed Extraction

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A Powerful Suite of Analysis and Extraction Tools

The tools designed by Silicon Frontline resolve your issues accurately and efficiently, with leading-edge performance and capacity required by today's sophisticated designs.

  • R3D: resistive 3D extraction and analysis
  • R3D Gate: analyzes and optimizes transient impact of gate networks
  • Ethan: full chip electro-thermal simulation of power devices
  • P2P: point-to-point IR drop analysis
  • ESRA: full chip ESD analysis
  • F3D: fast 3D extraction