Silicon Frontline will present the newest approaches for simulating and optimizing integrated circuits to correctly handle IR Drop, Electromigration and ESD challenges.
A Leader In
Power Device Analysis: Rdson calculation, Current Density & IR Drop Analysis, EM Verification, Gate delay Analysis, transient operation of power device and full chip, Transient Electro-thermal Analysis
IR Drop & EM Analysis: Resistance Mapping highlights weak points in networks, point to point resistance, Pre and Post LVS analysis, Static and dynamic analysis capabilities, Extremely simple set-up
ESD Analysis: Chip level Analysis providing HBM, CDM and MM support, Supports TLP measurements, Highlights non-esd device failures, Reports voltage, current density and resistances for all ESD events
Parasitic Extraction: Guaranteed Accurate parasitic extraction, user controlled accuracy achievable, Full chip capacity, Supports standard design flows, Supports Manufacturing Effects, Provides distributed Extraction