ERCheck is an electrical rule checker for pre- and post-layout netlists.

Key Features

  • Identifies user-defined circuit patterns in design netlist
  • Reports, for each instance, location (and device/port/net mapping)
  • Usable throughout the physical design process:
    • Reads SPICE and CDL format netlists

Comprehensive yet flexible

  • Provides templates for ESD-related checks


  • Unlimited capacity, fast, reliable
  • No need to write increasingly-elaborate scripts
  • Provides accessible and actionable results

Summary Report and Rules Details